1. Field of the Invention
The present invention relates to clocked circuits for processors. More particularly, the invention relates to a single-transistor-clocked circuit, more especially to a single-transistor-clocked flip-flop.
2. Description of Related Art
Power consumption is a constant concern in modern processors. Processor clock systems, consisting of flip-flops and latches, consume a large amount of power in modern processors. The clocked transistors within a flip-flop have 100% switch activity and present a huge load on the clock distribution network. If one can reduce the number of clocked transistors in a flip-flop, the clock tree will have less capacity load and hence reduce the power consumed in the clock network. This will further result in reducing the number and size of the clock driving buffers, which will in turn cause a significant reduction in the power consumption of the overall system.
One flip-flop well known in the prior art is the ep-DCO, which is described in Tschanz, J. et.al, “Comparative Delay and Energy of Single Edge-triggered And Dual Edge-triggered Pulsed Flip-flops For High-performance Microprocessors,” International Symposium on Low Power Electronics and Design, pages 147–152, 2001. Referring to FIG. 1, ep-DCO 100 comprises first branch 135 having transistors 102, 104, 106 connecting in series between first node 127, which is coupled to a high or logic one potential, and second node 117 which is coupled to a low, or logic zero potential. Second branch 133 is provided and includes transistors 108, 110, 112 connected in series between node 127 and node 117.
Inverter chain 119 and latches 121, 125 are also provided in the flip-flop circuit. Inverter chain 119 consists of three inverters connected in series. Clock signal CLK is received at input node 101, which is connected to one input of NAND 116 and the input of inverter chain, 119. Inverter chain 119 is connected in series between node 101 and node 129 and the output of inverter chain 119 is connected to one input of NAND 116. The output of NAND 116 is connected to inverter 114. The output of inverter 114 is connected to the gates of transistors 106, 110. Data signal D is received at data input 105, which is connected to the gate of transistor 104.
Node 107 is defined as the connection between transistors 102, 104. Node 107 is connected to the gates of transistors 108, 112 and to latch 121. Node 109 is defined as the connection between transistors 108, 110 and is connected to latch 125.
In one embodiment of ep-DCO 100, latches 121, 125 comprise back-to-back connecting inverters. Each latch is composed of 2 inverters, with one inverter being weaker than the other. In this embodiment, a latch will retain its value even if disconnected from the rest of the circuit.
In one embodiment of ep-DCO 100 transistors 102, 108 are P type transistors. A P type transistor turns on between its source and its drain when its gate is at a low potential and turns off when its gate is at a high potential.
In one embodiment of ep-DCO 100 transistors 104, 106, 110, 112 are N type transistors. An N type transistor is on between its source and drain when its gate is at a high potential and is open (off) between its source and its drain when its gate is at a low potential.
The operation of prior art flip-flop ep-DCO 100 of FIG. 1 is as follows. The rising edge on signal CLK at input 101 generates a positive edge at transistors 106, 110. The pulse width could be controlled by inverter-chain 119.
During the evaluation period, the clock pulse at node 103 feeds to transistors 106, 110. At the clock pulse rising edge transistors 106, 110 turn on. If the input D at node 105 is high, then transistor 104 is on. The NMOS stage of first branch 135 turns on. Node 107 pulls to GND. PMOS transistor 108 turns on and charges node 109. The signal at node 109 therefore pulls up to high.
Conversely, if the input D at node 105 is low, then transistor 104 turns off. The NMOS stack of first branch 135 will turn off as well. Signal X (the output of first branch 135 of ep-DCO 100) at node 107 is high because node 107 was pre-charged by the previous cycle. Transistor 112 turns on when the clock pulse is high, as will transistor 110. Node 109 will be pulled down to the low state.
During the pre-charge period (i.e. when clock signal CLK is low), transistor 102 is on and pulls signal X at internal node 107 to high. Transistors 106, 110 will turn off and both the NMOS stacks of the two branches are off. The output at node 109 is kept by latch (keeper) 125.
While flip-flop 100 is adequate for performing the clock function in a processor, it has limitations. There is constant and redundant switching activity at internal node 107. This undesirable switching activity occurs because node 107 is pre-charging and discharging even when D is kept high. Additionally, glitches appear at the output node that could cause noise problems in the subsequent circuits. Additionally, ep-DCO 100 consumes relatively large amounts of power because of the three clocked transistors that are used. Clocked transistors are those whose gates are connected to receive a clock pulse.
It is an object of the present invention to provide a flip-flop that minimizes redundant switching activity.
It is an object of the present invention to provide a flip-flop that prevents glitches at the output node.
It is another object of the invention to provide a flip-flop that consumes less power than current flip-flop devices.